珞珈山水BBS -- 单文区文章阅读

搜索

单文区文章阅读 [返回]
发信人: greenlights (长草，拔草，再长草), 信区: Job 标题: [Marvell]Staff ASIC Verification Engineer上海北京火热招聘! 发信站: 珞珈山水 (Thu May 5 16:15:08 2016), 站内美满电子，创芯世界！ Smart Life, Smart Lifestyle! 接触核心技术，全球无缝沟通,创芯世界，等你硅队！美满电子快速通道--投递简历至al-china-hr@marvell.com ,邮件标题格式为“姓名 -学校-意向职位-地点-珞珈山水”。 Job Title: Staff ASIC Verification Engineer Location: Shanghai/Beijing Department: Datastorage IC R&D Responsibility: Work together with algorithm team and design team to develop testplan and testcase for various blocks in our Read Channel products. Maintain and help improve our UVM based verification environment. Guide junior verification engineers to improve our verification coverage and reduce number of tape out. Research on some advanced verification technology such as assertion based formal verification. Requirement: Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 8+ years working experiences in ASIC verification. Familiar with System-Verilog and UVM verification methodology Familiar with script languages(perl,tcl,sh etc.) is a plus Familiar with digital signal processing knowledge is a plus Good problem solving and communication skills Good written and spoken English. Be able to work together with global team. -- ※ 来源:·珞珈山水 http://bbs.whu.edu.cn·[FROM: 222.73.125.*]
[返回单文区目录]

单文区文章阅读 [返回]

发信人: greenlights (长草，拔草，再长草), 信区: Job
标  题: [Marvell]Staff ASIC Verification Engineer上海北京火热招聘!
发信站: 珞珈山水 (Thu May  5 16:15:08 2016), 站内

美满电子，创芯世界！
Smart Life, Smart Lifestyle!

接触核心技术，全球无缝沟通,创芯世界，等你硅队！

美满电子快速通道--投递简历至al-china-hr@marvell.com ,邮件标题格式为“姓名
-学校-意向职位-地点-珞珈山水”。

Job Title: Staff ASIC Verification Engineer
Location: Shanghai/Beijing
Department: Datastorage IC R&D

Responsibility:
Work together with algorithm team and design team to develop testplan and testcase for various blocks in our Read Channel products.
Maintain and help improve our UVM based verification environment.
Guide junior verification engineers to improve our verification coverage and reduce number of tape out.
Research on some advanced verification technology such as assertion based formal verification.

Requirement:
Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 8+ years working experiences in ASIC verification.
Familiar with System-Verilog and UVM verification methodology
Familiar with script languages(perl,tcl,sh etc.) is a plus
Familiar with digital signal processing knowledge is a plus
Good problem solving and communication skills
Good written and spoken English. Be able to work together with global team.


--

※ 来源:·珞珈山水

http://bbs.whu.edu.cn·[FROM: 222.73.125.*]

[返回单文区目录]